The present invention relates to digital data processing hardware, and in particular to the design of transmission circuits for transmitting clock signals to components of a digital data processing system.
In the latter half of the twentieth century, there began a phenomenon known as the information revolution. While the information revolution is a historical development broader in scope than any one event or machine, no single device has come to represent the information revolution more than the digital electronic computer. The development of computer systems has surely been a revolution. Each year, computer systems grow faster, store more data, and provide more applications to their users.
A modern computer system typically comprises a central processing unit (CPU) and supporting hardware necessary to store, retrieve and transfer information, such as communications buses and memory. It also includes hardware necessary to communicate with the outside world, such as input/output controllers or storage controllers, and devices attached thereto such as keyboards, monitors, tape drives, disk drives, communication lines coupled to a network, etc. The CPU is the heart of the system. It executes the instructions which comprise a computer program and directs the operation of the other system components.
From the standpoint of the computer""s hardware, most systems operate in fundamentally the same manner. Processors are capable of performing a limited set of very simple operations, such as arithmetic, logical comparisons, and movement of data from one location to another. But each operation is performed very quickly. Programs which direct a computer to perform massive numbers of these simple operations give the illusion that the computer is doing something sophisticated. What is perceived by the user as a new or improved capability of a computer system is made possible by performing essentially the same set of very simple operations, but doing it much faster. Therefore continuing improvements to computer systems require that these systems be made ever faster.
A digital data processing device is a sequential state machine, in which state changes are regulated by signals from constant frequency oscillators, generally known as xe2x80x9cclocksxe2x80x9d. In fact, a large computer system may have many clocks. The overall speed of a computer system (also called the throughput) may be crudely measured as the number of operations performed per unit of time. Conceptually, the simplest of all possible improvements to system speed is to increase the clock speeds of the various components, and particularly the clock speed of the processor(s). E.g., if everything runs twice as fast but otherwise works in exactly the same manner, the system will perform a given task in half the time.
Clock speeds are limited by various design parameters, but in particular are often limited by the transmission length of clock lines. A clock signal which is distributed only within an integrated circuit chip can operated at a relatively high frequency. However, as the clock signal is distributed to physically more remote components, such as multiple chips on an electronic circuit card assembly, or multiple card assemblies attached to a common mother board, or multiple card assemblies or similar devices in separate packaging units, it is generally necessary to slow down the clock. Early computer processors, which were constructed from many discrete components, were susceptible to significant speed improvements by shrinking component size, reducing component number, and eventually, packaging the entire processor as an integrated circuit on a single chip. The reduced size made it possible to increase the clock speed of the processor.
A large computer system typically has multiple physical components, some of which may be physically located in different electronic circuit card assemblies or in different housings. Additionally, the internal design (and maximum clock frequency) of any single digital component will vary. If a common, universal clock frequency is used for an entire system, it must be slow enough to accommodate the slowest element of the system, making it necessary to slow down the faster components to match the common frequency. Furthermore, since it is desirable to support the attachment of component of multiple different types, it may be difficult to know the characteristics of all system elements in advance. For these reasons, the various components of a computer system are typically designed to operate on different respective internal clock frequencies, which are usually generated by the components themselves.
Separate asynchronous clocks in different components may be fine as long as each component performs its function oblivious to the others. However, where data is to be communicated from one component to another, at least some degree of synchronization is generally required for the communication. This means that at least one of the components will receive an externally generated clock signal for timing on a communications medium, such as a bus. Although much of the internal logic within the component might not use this external clock signal, at least some of the digital logic associated with the external communications interface will be driven by the external clock signal.
For any of various reasons, an external clock signal might be unavailable or unreliable. For example, during initial power-up and/or self-testing of a system, a component intended to receive an external clock signal may be ready before the component intended to generate the signal. Alternatively, service and maintenance operations performed on a component which generates the external clock signal may cause the clock signal to be temporarily lost or corrupted. Noise from any of various other sources, including service or maintenance operations on other devices, especially devices sharing the same communications bus, may have similar effects.
Ideally, the effects of a lost or degraded external clock signal should be limited to the communications medium which it synchronizes. However, this is not always the case. A lost or degraded clock signal may have unpredictable effects on the interface logic, which in some cases can cause unanticipated problems in portions of the component which are not synchronized to the external clock signal.
As the need for supporting a large variety of heterogenous devices in a single system environment grows, as well as the demand for constant availability and concurrent maintenance of systems, it can be expected that the circumstances under which distributed clock signals might be lost or degraded will become more numerous. It is desirable that a system recover as gracefully as possible from loss or degradation of a clock signal. However, the growing heterogeneity of system components and variety of environments makes it increasingly difficult to foresee all the consequences of lost or degraded clocks. Therefore, a need exists for improved techniques to prevent or alleviate the consequences of degraded clock signals.
An oscillator transmission switching circuit switches between asynchronous oscillator signals with low latency.
In one aspect of the preferred embodiment, the switching circuit has an operational mode, whereby during transition from a first oscillator to a second oscillator, the switching circuit transitions first to a bridge input immediately following an edge of the first oscillator, and holds the output at the bridge input until the same edge of the second oscillator is detected, at which the output switches to the second oscillator.
In another aspect of the preferred embodiment, control of the switching circuit is implemented as a state machine in a plurality of memory elements, which are preferably two-stage latches, which record a state, the latches providing control input to selection logic for selecting among a first oscillator input, a second oscillator input, and a bridge input. Preferably, a fast transition circuit (called a fast set/reset logic) provides the capability to by-pass the latch output under certain conditions for faster transition from one state to another.
Preferably, the bridge input logic level is selectable to accommodate conditions in which the first oscillator signal is stuck at either a logic 0 or a logic 1.
In the preferred embodiment, a fault detection circuit detects the loss or degradation of a primary oscillator signal and automatically triggers a switch to an alternate oscillator signal using the oscillator transmission switching circuit. The detection circuit can also trigger a return to the primary oscillator when the primary oscillator signal is restored. Preferably, a separate external signal can also trigger a switch from one oscillator to another oscillator.
An oscillator transmission switching circuit in accordance with the preferred embodiment of the present invention thus supports relatively seamless and rapid switching from one oscillator signal to another under a range of different asynchronous environments and causative conditions, minimizing disruption to downstream logic which relies on an oscillator signal.
The details of the present invention, both as to its structure and operation, can best be understood in reference to the accompanying drawings, in which like reference numerals refer to like parts, and in which: